1. Field of the Invention
The invention relates to improving the performance characteristics of charge carrying devices such as floating gate transistors utilized in flash memory devices, EEPROM, and other technologies.
2. Description of the Related Art
Flash memory devices have become an exceedingly popular form of data storage and are used in a multitude of applications where rapid access to data is required. Generally, a flash memory device comprises an array of electrically erasable memory cells. Each cell may be comprised of an EEPROM or EPROM floating gate transistor, with the cells organized in an array of columns and rows which are accessible by control circuitry on a row or column address basis. This is shown in FIG. 1, wherein two floating gate transistors 20 are shown coupled to column address logic 25 and row address logic 26. (FIG. 1 represents a NOR array; however, the invention discussed herein, and the principles discussed herein, are applicable to several types of memories.)
Flash EEPROM devices, and methods for making such devices, are well known in the art. In general, both the EPROM and EEPROM devices are characterized by a floating gate and an electrical connection to a control gate, both of which are fabricated out of bulk and other types of silicon doped with appropriate doping materials to render the silicon conductive. The flash EPROM device is characterized by charging of the floating gate using hot carrier injection and discharge of the floating gate device using Fowler-Nordheim tunneling, while the flash EEPROM device is characterized by the use of Fowler-Nordheim tunneling during both charging and discharge.
FIGS. 2A, 2B and 3A, 3B show a typical floating gate device 30. As shown therein, a silicon substrate 32 (in this embodiment a p-type silicon substrate), has formed therein an n+ source region 34 and an n+ drain region 36. A floating gate 38, generally comprised of deposited polysilicon or amorphous silicon, is shown overlying portions of source 34 and drain 36. A control gate 40 overlies floating gate 38. Two oxide regions 42, 44 separate control gate 40 from floating gate 38, and floating gate 38 from the surface of substrate 32, respectively.
As noted above, electrons are stored on floating gate in different ways, depending upon the type of device. FIG. 2A shows how charge is added to a typical flash EPROM cell through hot carrier injection. As shown therein, the control gate is typically coupled to +10 volts, the source to 0 volts, the drain to 5 volts, and the substrate to 0 volts. As a result, a conductive region across the channel is established and electrons accelerated into this region. Electrons are raised sufficiently in potential to overcome the insulating property of gate layer 42.
FIG. 2B shows the voltages used to add charge to the typical flash EEPROM cell by holding the potential of drain 36, source 34 and the substrate at 4 volts or 0 volts, and applying a pulse of approximately 10 volts to 18 volts to control gate 40 (depending upon whether the substrate region is a p-well or bulk silicon). Although not shown, in an EEPROM device a portion of the floating gate 38 is positioned above the tunnel dielectric closer to drain 36 than other regions of tunnel dielectric 44. The thin dielectric region coupled to the high voltage between the gate and drain produces Fowler-Nordheim tunneling of electrons into the floating gate 38.
FIGS. 3A and 3B graphically illustrate the discharge operation of a floating gate device in flash memory, which results in significant drain source and substrate current due to band-to-band tunneling in the gate-to-source overlap region. (For purposes of simplicity, in FIG. 3B, the control gate is not shown.) As should be readily understood, discharge of floating gate is one of the two most fundamental operations for any non-volatile memory device. It should be further recognized that the action of discharging electrons from the floating gate can be an erase function, where charging the floating gate is equivalent to writing a data bit to the gate, or it could be a write function, where all the bits are charged and then selectively discharged to show data on the gate.
As shown in FIG. 3A, in a typical discharge operation, the voltage of the source is 4 volts, the voltage at the control gate is (-)8 volts, the drain voltage is left floating, and the substrate 32 is coupled to ground. During this discharge operation, electrons on floating gate 38 should be drawn toward the source and vacancy holes along line 46 (FIG. 3B), to ground.
As shown in FIG. 3B, an alternative method for discharging the gate, the floating gate is held at (-)4 volts, the source voltage is held at +4 volts, and the drain is left floating. This condition is typical for memory arrays such as that shown in FIG. 1 wherein the entire array is being discharged simultaneously.
FIG. 3B shows conditions under which the band-to-band tunneling effect has been observed. The effect has been studied in several contexts to determine its effect on MOS transistors. In the case represented in FIGS. 3A and 3B, the desired effect is to drive electrons toward collection at the source region (as shown in FIG. 3B), while holes are collected in the substrate. A current has been found in MOSFETS at breakdown voltages much below what is usually considered the breakdown voltage of the device, typically in devices with thin oxides. See, Jian Chen, et al., Subbreakdown Drain Leakage Current in MOSFET, IEEE ELECTRON DEVICE LETT., vol. EDL-8, no. 11, pp. 515-517, November, 1987; T. Y. Chan, et al., The Impact of Gate-Induced Drain Leakage Current on MOSFET Scaling, IEDM TECHNICAL DIGEST, pp. 718-721, 1987; and Chi Chang, et al., Corner-Field Induced Drain Leakage In Thin Oxide MOSFETS, IEDM TECHNICAL DIGEST, pp. 714-717, 1987. Although solutions have been proposed which include establishing a minimum oxide thickness or limiting the voltage of the potential difference during discharge, such options are not advantageous or suitable for continued scaling of devices to ever smaller channel lengths.